The Space Based Radar (SBR) program includes a joint technology demonstration between NASA and the Air Force to design a low-Earth orbiting, 2?50 m L-band (1.26 GHz) radar system for both Earth science and intelligence-related observations. A key subsystem aboard SBR is the electronically-steerable digital beamformer (DBF) network that interfaces between 32 smaller sub-antenna panels in the array and the on-board processing electronics for Synthetic Aperture Radar (SAR) and Moving Target Indication (MTI). In this paper, we describe the development of a field-programmable gate array (FPGA) based DBF processor for handling the algorithmically simple yet computationally intensive inner-product operations for wideband, coherent beamforming across the 50 m length of the array. The core functions of the DBF?-the CORDIC (Coordinate Rotation Digital Computer) phase shifters and combiners?-have been designed in the Verilog hardware description language and implemented onto a high-density Xilinx Virtex II FPGA. The design takes full advantage of the massively parallel architecture of the Virtex II logic slices to achieve real-time processing at an input data rate of 25.6 Gbit/s. Tests with an antenna array simulator demonstrate that the beamformer performance metrics (0.07 degree rms phase precision per channel, -39.0 dB peak sidelobe level) will meet the system-level requirements for SAR and MTI operating modes.

We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.

Abstract- The Air Force Research Laboratory (AFRL) and the Jet Propulsion Laboratory (JPL) are collaborating in the technology development for a space based radar (SBR) system that would feature a large aperture lightweight antenna for a joint mission later in this decade. This antenna system is a 50m x 2m electronically steerable phased array in L-band (1260 MHz center frequency, 80 MHz bandwidth) and contains 384 x 12 Transmit/Receive modules. The radar is designed to operate in a variety of modes including Synthetic Aperture Radar (SAR) and Moving Target Indication (MTI). Stringent requirements are placed on phase center knowledge and antenna sidelobe levels during a data take, in the presence of temperature changes due to the orbital thermal environment, self heating, spacecraft platform vibrations, and mechanical deformation. We present an auto-calibration and metrology system concept to correct for phase errors and mechanical deformation during the mission.

This paper discusses beam-domain space-time adaptive processing (STAP) algorithms for a low-earth-orbit (LEO) space-baced radar (SBR). The performance of subarray-based joint-domain-localized (JDL) algorithm is first examined for various processor parameters. Then, a combined beam-domain STAP algorithm approach that combines JDL with difference ( beams is presented. It is shown that the combined JDL- algorithms offer less system complexity and yield performance similar to that of JDL that uses higher degrees of freedom. It is also shown that the earth?s rotation induces a crab angle to the platform, which makes the clutter range-Doppler spectrum vary with range. Illustrative examples show that this crab angle severely degrades the signal-to-interference-plus-noise ratio (SINR), thereby reducing the minimum detectable velocity (MDV) of STAP systems.

We are developing an on-board imaging radar data processor for repeat-pass change detection and hazards management. This is the enabling technology for NASA ESE to utilize imaging radars. This processor will enable the observation and use of surface deformation data over rapidly evolving natural hazards, both as an aid to scientific understanding and to provide timely data to agencies responsible for the management and mitigation of natural disasters. Many hazards occur over periods of hours to days, and need to be sampled quickly. The new technology has the potential to save many lives and millions of dollars by putting critical information in the hands of disaster management agencies in time to be of use. The processor architecture integrates two key technologies by combining a Field Programmable Gate Array (FPGA) front-end with a reconfigurable computing back-end. Through this approach we are able to capitalize on the strengths of both technologies for the optimization of performance while maintaining flexibility where needed within the algorithmic implementation. A searchable on-board data archive will store the reference data sets needed for change detection processing. In this paper, we will present an overview of the change detection processing algorithm and the preliminary hardware architecture.