2004 IEEE Radar Conference

Innovative Radar Technologies - Expanding System Capabilities

 April 26-29, 2004 Wyndham Philadelphia at Franklin Plaza Philadelphia, Pennsylvania
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Tutorial 3.4
Real-Time Embedded Computing for Signal and Image Processing Applications

Mr. David Martinez - MIT Lincoln Laboratory, Dr. Michael Vai - MIT Lincoln Laboratory, Mr. Robert A. Bond - MIT Lincoln Laboratory

Thu, 29 April 2004, 8:00 AM - 12:00 PM


In the last ten years, there has been significant emphasis on advancing sensor systems with active electronically-steered arrays (AESAs). The recent advances in computing technologies make it affordable to exploit the flexibility of AESA antennas using very high performance embedded computers for signal and image processing. This tutorial presents an overview of applications demanding real-time embedded computing, an introduction to hardware and software implementation techniques, recent advances in hardware and software standards to achieve rapid technology insertion, and a look into observed embedded computing trends.

A network-centric warfare implies leveraging information from multiple assets in-theater. However, communicating sensor data without significant processing on board the sensor platform would completely clog the available and future communication bandwidth. In the next ten to twenty years, AESA-based sensors will consist of 100 to 1000 sensor channels, with data rates exceeding hundreds of billion bytes per second (driven by analog-to-digital converter sampling rates). Therefore, on-board computation will be necessary to reduce data rates and to transform signal and image data into information. This information from ground, air, and space assets will then be routed across the theater and globally to permit extracting the requisite knowledge needed by our warfighters. The tutorial focuses on the sensor real-time computation to transform data into information demanding computations reaching and, in some cases, exceeding a trillion operations per second.

The tutorial will start by reviewing example applications centered on AESA architectures. These applications will highlight typical computation, communication, and memory requirements, constrained to implementations with stressing low size, weight, and power goals. After setting the application domain and on-board signal and image processing complexity drivers, implementation options are reviewed. The options range from custom application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), and general purpose processors. The tutorial material will include working through an FPGA design example using contemporary tools. The tutorial concludes with an introduction to embedded software practices and techniques. Particular emphasis is put on emerging software middleware standards and an open system architecture for real-time embedded systems.

This tutorial is designed for system designers, algorithm developers, hardware and software designers, and program managers interested in an overview and introduction to real-time embedded computing with emphasis on AESA antennas. The tutorial content will also address emerging trends in hardware, software, and rapid prototyping techniques. The tutorial draws from the authors? over fifty years of combined experience in these areas.

?This work is sponsored by DARPA under Air Force Contract No. F19628-00-C0002. Opinions, interpretations, conclusions, and recommendations are those of the author(s) and are not necessarily endorsed by the United States Air Force.?


Mr. David Martinez - MIT Lincoln Laboratory

Mr. David R. Martinez is Associate Division Head of the Sensor Systems Division at MIT Lincoln Laboratory. He received his Bachelor?s degree from New Mexico State University in 1976, and his M.S. degree from MIT, and the E.E. degree jointly from MIT and the Woods Hole Oceanographic Institution in 1979. He completed an M.B.A. from the Southern Methodist University in 1986. He was elected IEEE Fellow in 2003. He is actively involved in several projects focused on space-based technology, embedded digital systems, electronic steered phased arrays, and adaptive sensor signal processing. He joined MIT Lincoln Laboratory in 1988 and was responsible for the development of a large prototype space-time adaptive signal processor. This effort resulted in a large-scale demonstration of the world?s first real-time adaptive signal processor for future surveillance systems. Prior to joining MIT Lincoln Laboratory, he was Principal Research Engineer at ARCO Oil and Gas Company responsible for a multidisciplinary company project to demonstrate the viability of real-time adaptive signal processing techniques. He received the ARCO special achievement award for the planning and execution of the 1986 Cuyama Project, which provided a superior and cost-effective approach to 3-D seismic surveys. He holds three U.S. patents. From 1997 to 1999, he was the founder and chairman of a national workshop on high performance embedded computing. He has also served as keynote speaker at both the Real-Time Systems Symposium and the Second International Workshop on Compiler and Architecture Support for Embedded Systems. He has been appointed to serve on the Army Science Board since 1999. From 1994 to 1998, he was Associate Editor of the IEEE Signal Processing magazine.

Dr. Michael Vai - MIT Lincoln Laboratory

Dr. M. Michael Vai has more than 20 years of experience in high performance computing. Dr. Vai has worked and published extensively in very large scale integration (VLSI), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA), design methodology, and embedded digital systems. He has published 60+ technical papers and a 405-page book (VLSI Design, CRC Press, 2001). Dr. Vai received his B.S. degree from National Taiwan University, Taipei, Taiwan, in 1979, and his M.S. and Ph.D. degrees from Michigan State University, East Lansing, Michigan, in 1985 and 1987, respectively, all in electrical engineering. Until July 1999, Dr. Vai was on the faculty of Electrical and Computer Engineering Department, Northeastern University, Boston, Massachusetts. At Northeastern University, he developed and taught the VLSI Design and VLSI Architecture courses. He also established and supervised a VLSI CAD Laboratory. In May 1999, the Electrical and Computer Engineering students presented him with the Outstanding Professor Award. During Dr. Vai?s tenure at Northeastern University, he performed research programs funded by National Science Foundation (NSF), Defense Advanced Research Projects Agency (DARPA), and industry. Dr. Vai is currently a technical staff member at Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts. He is a key player in the embedded digital systems group of Lincoln Laboratory. He has designed and tested signal processing systems incorporating low power million-gate VLSI chips and FPGAs. In Spring 2002, Dr. Vai coordinated and taught a VLSI Design course at Lincoln Laboratory. In April 2003, Dr. Vai gave a lecture ?ASIC and FPGA DSP Implementations? in the IEEE lecture series ?Current Topics in Digital Signal Processing.? Dr. Vai is a senior member of IEEE.

Mr. Robert A. Bond - MIT Lincoln Laboratory

Mr. Robert A. Bond was born in Quebec, Canada in 1955. He has a B.S. (honors) in Physics from Queen?s University, Ontario, Canada. Mr. Bond has worked in the area of embedded processors and signal processing technology for over twenty five years. He joined MIT Lincoln Laboratory in 1987 and is currently Leader of the Embedded Digital Systems Group. He has expertise in both software engineering management as well as signal processing technology. At Lincoln Laboratory, Mr. Bond has led the development of several notable signal processing systems and has pioneered the use of portable middleware libraries and software engineering methods. He was responsible for the development of the Mountaintop RSTER radar software architecture and was coordinator for the radar system integration and verification. He was involved in early studies to evaluate the use of massively parallel processors (MPP) for real-time signal processing. In the late ?90s, he managed the development of an 85 Gflop/sec, 1000-processor MPP for performing radar space-time adaptive processing (STAP). This real-time software application consisted of over 200,000 lines of embedded signal processing and control software, and achieved an end-to-end efficiency of nearly 30%. In the last five years, Mr. Bond has directed research and development in advanced software techniques for embedded signal and image processing systems. During this time, he oversaw the development of the parallel vector library (PVL), a prototype middleware library for portable, scalable, embedded signal processing. Mr. Bond is the co-chair of the High Performance Embedded Computing (HPEC) Software Initiative (HPEC-SI) Applied Research working group, which is currently involved in defining a portable, parallel extension to the industry standard vector-signal-image processing library (VSIPL). Mr. Bond has also served as Chairman for the High Performance Embedded Computing (HPEC) Workshop for the last four years. His current research interests include advanced signal processing middleware, rapid prototyping methodologies, cluster computing, software optimization techniques, and parallel/distributed algorithms and architectures. In 2003, Mr. Bond received the MIT Technical Excellence Award for his ?technical vision and leadership in the application of high performance embedded processing architectures to real-time digital signal processing systems.? Prior to joining Lincoln Laboratory, Mr. Bond worked at Unisys Corporation on radar and sonar simulations for Naval command and control systems. He started his career in embedded processing at CAE electronics, where he worked on radar, navigation, and Kalman filter systems for flight simulators.

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